While no one wants to admit that Moore’s Law is dead, it’s getting harder and harder to improve process technology, and TSMC is in big trouble at 3nm.
TSMC once claimed that the 3nm N3 process can increase the integration density by up to 60-70% compared to the 5nm N5 process.
However, a recent TSMC paper admits that,The SRAM cell area of the N3 process is 0.0199 square microns, which is only 5% smaller than the 0.021 square microns of the N5 process!
To make matters worse, the so-called 2nd generation 3nm N3E process has a SRAM cell area of 0.021 square microns, which is no different from the N5 process!
The density of the transistors in this case is only about 31.8 million per square millimeter.
at the same time,The SRAM cell area of the Intel 7 process (formerly 10nm ESF) is 0.0312 square microns, while the Intel 4 process (formerly 7nm) has shrunk to 0.024 square microns, an improvement of 23%, which is nearly as much same as TSMC 3nm process.
Looking at it this way, there is some reason for Intel’s process name change.
In addition, some data show that with 2nm and later processes, the density of transistors will reach about 60 million per square millimeter, but so-called “forksheet” transistors are needed, and it will take several years to wait.
SRAM is generally used as a cache in modern chipssuch as the 81MB cache in the Ryzen 9 7950X, such as the 123MB cache in the NVIDIA AD102 core,They often require advanced process support, otherwise the area and cost will be greatly exaggerated.
In fact, the first step in testing a new process is generally to see if the SRAM size and density have been significantly improved.
It seems that the way chipmakers are increasingly using chiplets and various complex packaging technologies is right, and relying solely on process technology is becoming increasingly unfeasible.
