“TSMC Outlines 2nm Plans: N2 Process Technology and GAAFET Transistors”

The Taiwanese chip maker officially presented the technical process with 2 nm standards last summer. The production of semiconductors with these technological standards will begin in 2025. The main feature of the N2 process technology will be the transition from FinFET to circular gate transistors (GAAFET). This will reduce leakage currents, allow flexible adjustment of performance and optimize consumption. Another important feature of the N2 process technology was to move the chip’s power lines to the other side of the chip, which would mean decoupling the data and control bus from power.

As it is now becoming clear, the transfer of power lines is expected during the implementation of the N2P process, which will occur in 2026. From previous statements by the company, the first implementation of the idea could be expected in 2025. Spacing the power and data interfaces on different sides of the die solves a lot of problems. Thus, the power supply lines to the transistors will become shorter, which will reduce their resistance. Spacing the wiring will reduce the area of ​​the crystals, the lion’s share of which was eaten by transmission lines and interlayer contacts. Finally, although this is not all, mutual interference will decrease, which will affect the stability of the signal characteristics of the chips.

Reducing the area of ​​the crystal occupied by contacts and wiring will lead to a significant increase in transistor density. TSMC has previously stated that moving from a 3nm process to a 2nm process will increase transistor density by 10%. To date, the forecast has been improved to 15% and, in the case of the implementation of the N2P process, the density may increase by a two-digit amount, which the company has not specified yet. Moore’s Law will breathe one more breath before it dies.

The company did not say anything about the N2X process technology, which will be implemented in 2026 or later. We can assume that this will not be a very common proposal, while the N2P process promises to be the workhorse of the company at the 2nm stage of chip production.

The company also announced progress in the preparation of the basic 2-nm process technology. The performance of GAAFET transistors in the composition of experimental silicon reaches 80% of the target values. And this is two years before the start of implementation, which is very, very good. At the same time, the level of rejects in the production of 2-nm SRAM cells with a volume of 256 Mb decreased to 50% or less.

In general, the 2nm process will allow TSMC to improve transistor performance by 10-15% for the same power and complexity, or reduce power consumption by 25-30% for the same clock speeds and number of transistors. On paper, TSMC is a year or two behind Intel, and the success of one company haunts the other. If each of them keeps their promises, then TSMC chips with GAAFET transistors will appear two years later than similar Intel chips (20A), which also concerns plans to move power lines to the back of the chip.