SSD capacity could quadruple by 2029 – 8TB NAND brings larger, more affordable drives to market

Since the advent of 3D NAND about ten years ago, SSD capacity has grown rapidly while the price per GB has gradually decreased. This is why most PCs today use SSDs. IEEE believes that this trend will continue in the coming years, increasing SSD storage capacity at least fourfold by 2029.

The reason that 3D NAND increases multidimensional capacity. On the one hand, the number of active NAND arrays has increased over the years, and on the other hand, the number of bits stored in one NAND memory cell has increased from two to three (three-level cell, TLC) and four (four-level cell, QLC). Both innovations emerged over time and were carefully measured to achieve economic objectives regarding TB costs.

2TB QLC NAND memory devices are already available for use in some mainstream 2TB SSDs, giving them 2TB of available storage space. The IEEE roadmap taps 4TB 3D NAND devices by 2027, doubling the capacity of common SSDs. Capacity is then expected to quadruple in 2029 as the industry moves to 8TB NAND memory devices. With this, we can expect the capacity of common SSDs to quadruple by 2028, although we are speculating.

Regarding the number of active layers, we are somewhere between 200 and 300 layers, depending on the manufacturer, but IEEE predicts more than 500 by 2027. Then companies like Samsung and SK hynix pre- reported more than 1000 series, but the prestigious institute decided not to predict this number.

Unlike predictions for the evolution of hard drives, the IEEE International Roadmap for Big Data Storage Devices and Systems is vague about what should be achieved in terms of storage density. And the number of active NAND layers and other NAND memory architectures. IEEE doesn’t even call QLC QLC; it’s called TLC+, probably meaning capabilities beyond even QLC (4-level charge), maybe a 5-level charge PLC (five-level cell).

“The way to increase the die density more and reduce the cost per bit includes reducing the growth of the number of layers, increasing the density of memory cells per layer (increasing the write density per layer), reducing the size of the holes that contain the memory cells. are subtracted, increasing the number of bits stored per transistor [от трехуровневой ячейки (TLC) до QLC и PLC]and maintains a high spin ratio per memory hole. These are design and manufacturing issues that must be addressed to maintain the high output necessary for profitable production. “