Because the discussions began to recur that Alder Lake it will not support SMT / HT, ie the processing of two threads per core, it will not go back to the situation and briefly summarize how it is.
To release the Intel processor generation Alder Lake it will not occur until the second half of the year, so almost all the information remains unofficial – yet the overall picture is quite clear and there does not seem to be anything that could change about it.
Intel folds Alder Lake of (up to) eight large x86 cores Golden Cove. These large cores are a direct successor to architecture Willow Cove used in mobile processors Tiger Lake. Willow Cove is a competitor Zen 3 (IPC seems to be very similar on average), so Golden Cove with the expectation of ~ 20% increase in IPC will be about at a similar level as Zen 4, where intergenerational ~ 20% is also expected.
These cores (Golden Cove v Alder Lake) in the basic concept is no different from previous generations – it is a powerful x86 architecture supporting SMT / HT, ie processing of two threads with one core.
Large cores Golden Cove will be supplemented by up to eight small x86 nuclei (formerly collectively referred to as Atoms) and specifically a new generation called Gracemont. Atoms, as has been the custom for many years, do not support SMT / HT, so one nucleus = one strand.
8 × Golden Cove (= 16 threads) + 8 × Gracemont (= 8 threads) = a total of 16 cores and 24 threads
What leads to such a Intel solution? There can be three reasons:
Strengths of Alder Lake
1. Small cores have significantly lower consumption or better consumption / performance ratio. In a situation where the multi-core performance of Intel processors is limited by power consumption, it may be more advantageous to devote, for example, 20 watts to eight small cores than to one large core. If the application is able to run efficiently on multiple cores, it brings extra performance without significant extra energy requirements.
2. Small cores have significantly lower demands on the silicon area. The area that would be taken up by one large core can be used by up to about four small ones. This is advantageous in a situation where production capacities are limited by the area of processed silicon (wafers).
3. This allows Intel to release a new architecture on an older process. While AMD’s Zen 4 is waiting for a new generation of process (5nm TSMC), Intel can release the novelty on a 10nm process (about the equivalent of 7nm TSMC), because the large cores, which take up most of the area and generate most of the heat, are half those of AMD processors.
On the other hand, such a solution also has disadvantages:
Weaknesses of Alder Lake
1. To create a single processor, you need to develop two architectures, which costs some extra money and splits the development tools into two branches.
2. The development of two architectures carries a higher risk of delay. It is enough for one of the architectures to be delayed and the release of the processor must be delayed.
3. Small kernels do not support all instruction sets as large kernels. If the application allows the use of such an instruction set, then either Intel can shut down small kernels (and use only large ones, which adds to the benefit of multi-core performance), or the processor can report that it does not support the instruction set. Then all cores will be used, but without the performance bonus of the advanced instruction set.
4. Although the combination of large and small cores can work well in a number of benchmarks – they are usually designed for a single-core test (which runs on one large core) and the load of all cores (when all large and small cores are used), in practice situations where the application can effectively use more than one core, but less than the full number of cores. For example, if an application can make efficient use of four cores, then let’s say mobile Alder Lake with two large (Golden Cove) and eight small (Gracemont) cores will perform worse than a hypothetical quad – core Golden Cove, which would cost a comparable amount of silicon and have a comparable consumption. Alder Lake thus, it will achieve maximum efficiency in a situation with a load of a low number of cores and also with a load of the maximum number of (all) cores. If there is a load somewhere in between, especially if the application is able to use more cores than the number of large cores (but not the entire processor), the efficiency will be lower.
But with all the advantages and disadvantages of this concept, Intel will get a processor that will be able to reach the market sooner than AMD, will be able to achieve higher single-core performance at the time of release than AMD’s offer at the time (Zen 3) and will be able to compete with at least twelve-core models Zen 3. Which are the three essential elements that s Comet Lake and Intel failed, thus three major shifts in competitiveness.
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