When Nvidia unveiled the Geforce RTX 3000 series with the “Ampere” architecture, the number of CUDA cores soared, something that during the event, to say the least, also surprised SweClockers editors. The large increase turned out to be due to Nvidia changing how the number of cores is calculated, as the capacity of the new graphics card calculation units (SM) did not really correspond to previous models with the “Turing” architecture.
With the next generation of graphics cards, which are expected to be the Geforce RTX 4000 series and the “Ada Lovelace” architecture, the number of CUDA cores can skyrocket once again. Already at the end of 2020 circulated data that the top model AD102 can get as many as 18,432 pieces, data that reappeared in connection with data leaks after Nvidia was subjected to a cyber attack.
|
Graphics circuit |
AD102 |
GA102 |
AD103 |
GA103 |
|---|---|---|---|---|
|
Technical |
5nm TSMC |
8nm Samsung |
5nm TSMC |
8nm Samsung |
|
SM cluster |
144 st. |
84 st. |
84 st. |
60 st. |
|
CUDA cores |
18 432 st. |
10 752 st. |
10 752 st. |
7 680 st. |
|
L2 Cache |
96 MB |
6 MB |
64 MB |
4 MB |
|
Memory bus |
384-bit |
384-bit |
256-bit |
320-bit |
–
This time, it is not only specifications for the top circuit AD102 that are looking out. In a table like circulating on Twitter specifies the number of SM clusters for the entire lineup of circuits. Provided that Nvidia does not once again change how the number of CUDA cores is calculated, it gives almost double the number for the top circuit in full-fledged design.
|
Graphics circuit |
AD104 |
GA104 |
AD106 |
GA106 |
AD107 |
GA107 |
|---|---|---|---|---|---|---|
|
Technical |
5nm TSMC |
8nm Samsung |
5nm TSMC |
8nm Samsung |
5nm TSMC |
8nm Samsung |
|
SM cluster |
60 st. |
48 st. |
36 st. |
30 st. |
24 st. |
24 st. |
|
CUDA cores |
7 680st. |
6 144 st. |
4 608 st. |
3 840 st. |
3 072 st. |
3 072 st. |
|
L2 Cache |
48 MB |
4 MB |
32 MB |
3 MB |
32 MB |
2 MB |
|
Memory bus |
192-bit |
256-bit |
128-bit |
192-bit |
128-bit |
128-bit |
–
For the middle segment and the simpler circuits, the increase is not as dramatic. On the other hand, something that stands out is a substantial increase in L2 cache, something that has found its way into the same leak. It states that Nvidia will increase the upper segment’s 6 MB and 4 MB respectively to 96 MB and 64 MB, with corresponding increases for the middle segment.
At the same time as the amount of L2 cache goes up, the memory bus is instead slimmed down a bit for everyone except AD102, which is somewhat reminiscent of how AMD does with Infinity Cache. The extended cache size certainly does not reach the same amount as AMD’s Infinity Cache, but in return Nvidia is investing in a large L2 cache instead of L3. It usually has lower latencies and higher bandwidth than its L3 ditto, but as with all types of storage, transfer speeds can not completely replace the amount of memory or vice versa.
As Nvidia has not yet taken the leaf out of its mouth regarding any of the specifications, they should be taken with a pinch of salt. Despite the multiple leaks that have been discovered in recent days, there is no reliable evidence for both if and what data actually originates from the graphics card giant’s servers.
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