Compatibility with SiSoft applications is not yet fully fine-tuned, some parameters are obviously detected incorrectly, such as 190GHz. But most correspond to the given description or range of expected values.
It looks like the listing comes from some test platform that was allowed 150W TDP (such models apparently won’t go on the market, Meteor Lake will be released for laptops only). However, we learn that this processor is equipped with a 128MB cache. We have been hearing for several months now that Intel is experimenting with the so-called Adamantine Cache with capacities of 128-512 MB. Apparently, this should be integrated in a silicon substrate on which individual functional tiles (chiplets) are mounted. 128 MB would be the smallest capacity from the tested range, on the other hand, it cannot be expected that a higher capacity could fundamentally benefit performance.
We also learn that the integrated graphics of this sample carries 64 EUs reaching up to 1.9 GHz. In May, information was leaked about a model with 128 EUs reaching up to 2.1 GHz. The sample we are talking about now could be Meteor Lake-P (a series focused on the performance of processor cores) and the May version Meteor Lake-U for economical laptops without a separate graphics card (thus a more powerful integrated core).
According to the information so far, it seems that the graphics with 128 EU should achieve roughly comparable performance to the APU Phoenix (now it is not about whether it will be slightly slower or faster, we will deal with integer multiples or fractions of power). If Intel’s 128 EU can be compared to iGPU Phoenixu, then logically Intel’s EU 64 will achieve significantly lower (theoretically half) performance than iGPU Phoenix. It will probably be more, Intel’s iGPUs do not scale linearly with the increasing number of EUs. If AMD to achieve the graphics performance that APU has Phoenixit doesn’t need graphics L4 cache and even L3 cache, then the question is why there is a variant Meteor Lake with 64 EU equipped with 128MB L4 cache. However, Intel’s strategy will probably be built the other way around: If the Meteor Lake architecture requires a silicon pad to connect the tiles, which costs something, then why not integrate the 128 MB cache into it? This silicon will be there anyway, so it can be used like this, although it probably won’t have any major benefit for most applications.
So where can Adamantine Cache benefit from the competition? The performance of the integrated graphics itself will be roughly comparable in the version with 128 EU, so there probably won’t be any major advantage over the competition. In terms of processor power, it’s more complicated. As we know from the V-cache tests of AMD processors, most applications do not benefit much from a large cache, but there are those for which the benefit is great. However, these mostly fall into the realm of servers or powerful workstations, but where Meteor Lake not aiming. Another area is games: A large processor cache is beneficial for obtaining maximum FPS from the most powerful graphics cards. However, Meteor Lake is aimed both at Ultrabooks (without a separate GPU), where this advantage remains at the theoretical level, and also at notebooks with separate graphics (Meteor Lake-P), where, of course, you cannot expect pairing with something at the level of a desktop GeForce RTX 4080 / 4090 / Radeon RX 7900 XTX. So there will be some benefits, but they will most likely be very specific situations, i.e. a benefit outside of 90% of normal loads. However, it is possible that the presence of a larger L4 cache can save some data transfers and thus reduce the energy requirements of the processor under certain types of load.
Intel is expected to make an announcement Meteor Lake 19.-20. September at the Innovation 2023 event with availability in the following (fourth) quarter. According to available information, these processors will consist of five pieces of silicon:
interposer with Adamantine cache processor tile (Intel 4) – up to 6 large + 8 small cores integrated GPU (TSMC N5 or N4) SoC / chipset (TSMC N7 or N6) – up to 2 small IO cores (TSMC N7 or N6)
In the maximum configuration, 6 large and 8+2 small cores are expected, of which the separately mentioned pair will be physically integrated in the SoC tile so that the processor tile can be turned off in the idle state to save energy.
2023-06-27 22:07:12
#Meteor #LakeP #128MB #cache #GHz
