Intel Raptor Lake processors are said to have larger L2 and L3 caches, and game performance can increase a lot

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The game performance of Intel processors is to increase in the next generation of Raptor Lake, which will be released at the end of this year. We have a first look at what that might be.

In the second half of the year, Intel will release the Raptor Lake processors, today’s successor generation Alder Lake. Hybrid architecture will be used even more strongly in this generation, but it will also have improved gaming performance. One of the first leaks promised to change the cache for this purpose, but so far we did not know what it meant. Maybe now: according to rumors on the Internet, Intel also wants to bet on high capacities like AMD, albeit a little differently.

These reports are not yet from a fully proven source, but they sound relatively likely. Gossip appeared on Twitter on Friday, according to which she will be a change in the cache already indicated by leaked documents from VideoCardz (which, on the other hand, is usually a very reliable source), different from the concept that AMD is coining. It has increased the L3 cache to 32 MB for Zen 3 and now even plans to increase it further Ryzenu 7 5800X3D s 3D V-Cache. But Intel seems to be increasing the L2 cache instead.

Larger L3 cache due to more cores

Raptor Lake, which will be sold as a 13th generation Intel Core (ie Core i9-13900K, for example) is supposed to have “68 MB total cache”, which includes L2 and L3 cache, not L1 core cache (it sounds illogical, but it is used that way, AMD also in the specifications usually writes the sum of L2 and L3). Just over half of it will be an L3 cache. Raptor Lake is reportedly not planning to change it, it will still be formed in a distributed manner, with each core or, in the case of small cores, a quad-core cluster forming one stop on the ring bus to which the L3 cache block is connected. When storing data in the cache, the processor distributes the data between the individual L3 cache blocks (this should probably be deterministic according to some hash address).

The capacity of the L3 cache per one block does not change. In Alder Lake it is 3 MB / block and the same will be said for Raptor Lake. However, the overall capacity will increase despite the unchanged architecture, as Raptor Lake will have more cores. The number of P-Core (large cores) will still remain the same eight with 16 threads, which will give eight 3MB blocks, but Raptor Lake will have exactly 16 E-Core in four clusters (instead of two clusters / eight E-Core cores). These four clusters will add four more 3MB blocks, so the total L3 cache will be 36MB, while at Alder Lake it is 30MB. It is likely that the effective latency may increase slightly, as more ring bus stops mean that the average data access latency is slightly higher.

However, this applies to the highest model with 8 + 16 cores. The capacity of the L3 cache for trimmed cheaper models will probably depend on the number of cores and E-Core clauses they will have active (although there seem to be exceptions to this, according to anomalous Core i5-1490F).

More: Intel Alder Lake has historically the most advanced x86 core. Golden Cove CPU architecture analysis

Velká L2 cache in P-Core and E-Core

So the main change for Raptor Lake will be in the L2 cache, which will have directly increased capacity for each core. For large P-Core cores, they will remain private, ie reserved for one core, but the capacity will increase from 1.25 MB for Tiger Lake and Alder Lake to 2 MB for each P-core.

This will increase the size of the working dataset that the kernel will be able to keep very close to, so that gaming performance could actually be improved. However, if latency deteriorates at the same time (the number of cycles that elapse before data can be accessed), some performance degradation may occur elsewhere.

68M cache is interesting.😄

— Raichu (@OneRaichu) January 14, 2022

In older leaks, there was information that the large cores in Raptor Lake have the designation “Raptor Cove” and should therefore be changed against Golden Cove, reportedly having some percentage higher IPC (power at 1 MHz). Those changes could theoretically consist of a larger L2 cache, which was also an architectural change between Ice Lake processors / Sunny Cove cores a Tiger Lake/Willow Cove. Intel could repeat this strategy, but it is quite possible that this time it will not be satisfied with it and will manage to make some beneficial changes outside the L2 cache.

However, the L2 cache will also be increased on small E-Core cores. Although the Gracemont architecture is still to be used for them (unfortunately no “Raptormont”…), it will still be a larger L2 cache. The Gracemont architecture uses L2 caches, which are always shared for the entire quad-core cluster, while Alder Lake uses a 2 MB implementation.

But Gracemont also supports a 4MB configuration from the start, and Raptor Lake is said to be using that capability. Sixteen E-Core cores will therefore have a total of 4 × 4 MB L2 cache. Thus, together, the L2 cache will be 32 MB, and under multithreaded loads, each thread will actually have the same average L2 capacity (1 MB), which could be important for balanced performance in some tasks. However, a larger L2 cache could also increase the general IPC of Gracemont cores, just as perhaps the increase of the Raptor Cove IPC cores.

More: Intel Gracemont CPU Architecture Analysis: Alder Lake’s “small cores” are stronger than you expect

Raptor Lake in “full fire” with 8 + 16 cores will have a total of 68 MB L3 cache. However, if the games run only on large cores and not on small ones, then they will not use the 16MB L2 cache in small cores. However, they will have a 12MB part of the L3 cache, which is associated with small cores. An application running exclusively on large kernels will therefore have 16 MB of L2 (in total) and 36 MB of L3 cache, for a total of 52 MB.

Both competitors increase the cache

By the way, the increase of the L2 cache will also take place at AMD. The current state of knowledge from leaks speaks quite clearly that the Zen 4 architecture will bring 1MB of L2 cache. This will be the first time that this has changed for the Zen core line. so far, all generations have had a 512KB L2 cache with a relatively low latency of 12 cycles (with the exception of the Ryzens 1000, where this apparently could not be put into operation and the cache runs in a somewhat slowed down mode with a latency of 17 cycles).

More: The first details of Zen 4 have been leaked. Increased L2 cache and TLB, AVX-512 support, maybe even ALU count

Resources: OneRaichu (Twitter)