HCB application required to improve memory cell array efficiency
“Like NAND, DRAM will be separated into peripherals to increase integration.”
Tech Insights Fellow Jeong-dong Choi presented on the current status and trends of memory semiconductor technology at ‘SEMI Member Day 2023’ held at the Suwon Convention Center on the 11th.
It is predicted that hybrid bonding may be introduced in the DRAM process in the future. This is to increase capacity by increasing DRAM integration. When hybrid bonding is introduced, it is expected that mass production of 64Gb or higher DRAM products will be possible.
Tech Insights Fellow Jeong-dong Choi presented on the current status and trends of memory semiconductor technology at ‘SEMI Member Day 2023’ held at the Suwon Convention Center on the 11th.
Fellow Choi said, “The memory cell array efficiency of products such as LPDDR5X only accounts for about 50%,” and added, “Like in the case of NAND, integration can be maximized by making a DRAM array die and making peripherals separately.” .
Peripheral, which Fellow Choi talked about, is responsible for logic in the DRAM area. Until now, logic circuits have been included inside DRAM. The idea is to separate them and increase memory cell density. In the case of current NAND, the peripheral has been moved to the bottom of the memory cell to increase integration.
Hybrid bonding is a technology that is attracting attention as a next-generation packaging technology. It has the advantage of being able to improve input/output (I/O) and wiring length by attaching wafers and heterogeneous chip dies. It is known that companies such as Samsung Electronics, SK Hynix, and Intel are preparing to introduce it.
Fellow Choi said, “In China, we produced products by applying hybrid bonding to CMOS logic and DRAM dies, and they are currently on the market. If we apply this concept, Samsung Electronics and SK Hynix will also be able to produce 32Gb dies.” explained.
Next-generation memory trends such as 3D DRAM were also introduced. He said, “There is a lot of talk (in the industry) about the difficulty of developing 3D DRAM,” and added, “Unlike Gate All Around (GAA) or NAND, if 3D format is applied to DRAM, homogeneity issues will 100% occur.” He added, “Due to difficulties in resolving the issue of uniformity, the industry is more active in developing 4F Square.”
The industry believes that Samsung Electronics is focusing on 4F Square, and SK Hynix and Micron are focusing on 3D DRAM to develop next-generation memory.
4F Square is a cell array structure that Samsung Electronics is currently researching. It is known that the chip die area can be reduced by about 30% compared to 6F Square. Currently commercialized DRAM has a 6F square structure, and it is known that there are structural difficulties in commercializing DRAM under 10nm. The industry estimates that the introduction of 4F Square, which can significantly reduce the die area, is one of the keys to solving the limitations of miniaturization.
The Elec = Reporter Noh Tae-min [email protected]
《The Elec, specialized media in the fields of semiconductors, displays, batteries, automotive electronics, and ICT parts》
Copyright © THE ELEC, a media specializing in electronic components. Unauthorized reproduction and redistribution prohibited.
2023-10-12 01:19:31
#Hybrid #bonding #applied #DRAM
