PCIe 5.0 is one of the innovations that will bring Intel Core 12th generation processors / Core 12000 / Alder Lake. Others include the new x86 core architecture with significantly higher IPC, a combination of large and small cores, the Intel 7 manufacturing process (renamed 4th generation 10th process), the LGA1700 / 1800 socket, and the DDR5 controller. Although he still needs a little tweaking.
PCIe 5.0 – Like PCIe 4.0, PCIe 3.0 or PCIe 2.0 doubles the baud rate per line (compared to the previous generation). Compared to the previous generation, however, Intel only equips it with a lower number of lines, specifically it looks like 8-16 PCIe 5.0 lines per processor. A lower value will probably apply to mobile models, higher to desktop models. For example Rocket Lake has PCIe 4.0 lines 20: 16 for graphics and 4 for example for M.2 SSD. Similarly, almost 2 years older, Zen 2 has 20 PCIe 4.0 lines in the desktop version: also 16 for graphics and 4 for storage.
Alder Lake differs: It has only 16 new generation lines (PCIe 5.0), which are designed primarily for × 16 slot (graphics) and no lines for storage (or other use) are present.
Situation when mounting a PCIe SSD on part of the lines
In principle, it will probably be possible to split the lines and use 8 PCIe 5.0 lines for the primary × 16 slot (graphics) and 8 PCIe 5.0 lines for the secondary × 16 slot (for future PCIe 5.0 SSDs or card / reduction to multiple PCIe 4.0 SSDs). However, the use of such a configuration is limited or counterproductive due to several factors.
First of all, we must realize that on a high-end platform, many users will use a powerful graphics card. There will be 8 PCIe 5.0 lines left. But graphics cards with PCIe 5.0 from AMD and Nvidia are not on the market and will not be in a year. In such a situation, it is secondary that the lines support PCIe 5.0 mode, as they will have to work in 4.0 mode (eg GeForce RTX 3080, Radeon RX 6800 XT) or 3.0 (eg GeForce RTX 2080 Ti). At that time, we have 5.0 lines, but since it will run in 4.0 or 3.0 mode and there are only 8 of them, the baud rate between the system and the graphics card will be half that if we put the card in an assembly with Rocket Lake, Zen 2 or Zen 3:
| ×1 | ×2 | ×4 | ×8 | ×16 | |
|---|---|---|---|---|---|
| PCIe 1.0 | 0,3 GB/s | 0,5 GB/s | 1 GB/s | 2 GB/s | 4 GB/s |
| PCIe 2.0 | 0,5 GB/s | 1 GB/s | 2 GB/s | 4 GB/s | 8 GB/s |
| PCIe 3.0 | 1 GB/s | 2 GB/s | 4 GB/s | 8 GB/s | 16 GB/s |
| PCIe 4.0 | 2 GB/s | 4 GB/s | 8 GB/s | 16 GB/s | 32 GB/s |
| PCIe 5.0 | 4 GB/s | 8 GB/s | 16 GB/s | 32 GB/s | 64 GB/s |
red: baud rate when using 8 Alder Lake lines with current GPUs
green: baud rate when using 16 Rocket Lake / Zen 2 / Zen 3 lines with current GPUs
Dividing lines is therefore the case Alder Lake considerably counterproductive, as the GPU will have half the transfer rate of current PCIe 4.0 platforms.
PCIe 5.0 and graphics cards
As already mentioned, PCIe 5.0 graphics from AMD and Nvidia have been waiting for generations RDNA 3 a Lovelace, which can go on the market in October 2022 at the earliest. In the second half of the coming winter, ie in the first quarter of 2022, we could see PCIe 5.0 on Intel Xe / Arc graphics. However, they aim at the maximum level of GeForce RTX 3070. Not that it would be poor in terms of performance, it may be enough for many users. But the GeForce RTX 3070 performance card will suffice not only with PCIe 4.0, but the GeForce RTX 2080 Ti (which is not slower) from the generation Turing did not have a problem with PCIe 3.0 either. So buy Alder Lake due to PCIe 5.0 on the future Xe does not make sense, because the GPU of this performance will work not only without PCIe 5.0, but also without PCIe 4.0 on sixteen lines.
PCIe 5.0 and storage
Platform Alder Lake it will not be equipped with a PCIe 5.0 M.2 slot, as the processor has no lines for it (the slot will remain with the current 4.0 generation). The desktop SSD disk designed specifically for the PCIe 5.0 slot has not been announced yet (so far only talk about server products, which should appear in about a year). The discussion asked whether it would not be possible to use the PCIe 5.0 slot in combination with the reduction to M.2 PCIe 4.0 disks. Of course you can, but it doesn’t make good sense.
If we divide the PCIe 5.0 lines as described above (8 × for graphics, 8 × for reduction), we will lose the baud rate on the graphics (instead of 64 GB / s PCIe 5.0 × 16, the graphics will be available for the reasons described above 8 -16 GB / s) and the reduction in the secondary slot degrades the 8 lines there (originally 32 GB / s) to 16 GB / s, because the current reductions are PCIe 4.0 and therefore work with half the transfer rate. The first reductions with PCIe 5.0 support may theoretically appear in the second half of next year at the earliest (the first products with a PCIe 5.0 controller are coming at that time), rather later, in 2023. So we don’t get anything we can’t achieve on current boards and lose graphics card baud rate.
PCIe 5.0 desktop platform Alder Lake thus it will be unusable at the time of its release (there will be no other PCIe 5.0 product on the market this year), very limited use in the first half of 2022 (there will be only PCIe 5.0 Xe graphics, given their performance, which was already in the PCIe 3.0 era, PCIe 5.0 will be somewhat redundant) and in terms of 2023, when there will be some PCIe 5.0 SSDs, the implementation on the platform Alder Lake seems to be an overly compromise, as the PCIe 5.0 solution for the M slot is not supported by this platform and by installing a PCIe 5.0 slot it degrades the graphics bit rate too much, unless PCIe 5.0 graphics are explicitly installed. If it was to be a so-called “future-proof” solution, it lacks 4 more PCIe 5.0 lines usable for storage or other devices. These would provide the ability to fit a PCIe 5.0 drive into the M-slot and prevent the primary sixteen lines from being split (degrading the baud rate when installing current graphics) between multiple devices.
PCIe 5.0 on Alder Lake apparently it was not aimed at the desktop, but at the mobile segment. There, a 2x faster interface will reduce the number of lines between the processor and the mobile GPU (Xe / Arc) by half, thus saving PCB space and reducing space requirements for the implementation of separate graphics, which is desirable and valued in the notebook segment.
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