After drop tests, now the Taiwanese semiconductor giant ad, that 3nm lithography (designated N3) was launched in a big way. According to TSMC, the yield is good, but the company did not specify the percentage of waste and which chips are good.
The most advanced process is currently available at the Fab 18 factory in Tainan, but the company is also counting on the upcoming Fab 21, which will be built in Arizona, USA. It will be built in 2024, but it will take another two years before it is equipped and operational. TSMC has invested $40 billion in the project.
Chips made using N3 will have significantly better parameters than N5 or its N4 derivative. According to TSMC, the density of the logic circuits has increased by 70%, but the memory circuits no longer scale so well, there is only a 5% shift. Additionally, the N3 can achieve up to 15% higher clock speeds or up to 30% less power consumption at the same frequencies.
In the first half of next year, the N3E derivative process will arrive, which will slightly reduce the density, but improve the operational properties. The N3 family will be very broad overall. TSMC is also preparing N3P, N3S and N3X for the next few years, which need to be optimized for performance and density.
Therefore, this year the manufacturer also introduced FinFlex technology, which will allow using transistors of different types on one chip so that each circuit uses a shape that is most suitable for it. For example, an SoC requires a CPU with the highest possible frequencies, but an integrated GPU will benefit more from more parallel drives, so higher density will benefit.
| Process | Density | Performance | Consumption | Serial production |
|---|---|---|---|---|
| N7 (DUV) | +70% compared to 16FF+ | +30% compared to 16FF+ | -60% compared to 16FF+ | Q2 2018 |
| N7P (DUV) | like N7 | +7% on N7 | -10% compared to N7 | ? 2019 |
| N7+ (EUV) | +17% on N7 | +10% on N7 | -15% compared to N7 | Q2 2019 |
| N6 | +18% on N7 | like N7 | like N7 | Q1 2020 |
| N5 | +80% on N7 | +15% on N7 | -30% compared to N7 | Q2 2020 |
| N5P | like N5 | +7% compared to N5 | -10% compared to N5 | ? 2021 |
| N4 | +6% on N5 | like N5 | like N5 | ? 2022 |
| N4P | +6% on N5 | +11% on N5 | -22% compared to N5 | ? 2023 |
| N4X | ? | +15% on N5 | ? | ? 2023 |
| N3 | +70% compared to N5 | +15% on N5 | -30% compared to N5 | H2 2022 |
| N3E | +60% compared to N5 | +18% compared to N5 | -34% compared to N5 | Q2 2023 |
| N3P | ? | ? | ? | ? 2024 |
| N3S | ? | ? | ? | ? 2024 |
| N3X extension | ? | ? | ? | ? 2024 |
| N2 | ? | +15% compared to N3E | -30% compared to N3E | ? 2025 |
TSMC is already fulfilling orders for the first customers, but the company won’t name who that is. In recent years, however, Apple has been the first to book new processes in advance. There are already rumors that they will be building the mighty M2 Pro and Max models on the N3.
The N3 process is the last one that will still use FinFET-type transistors, with N2 it will already switch to more advanced GAAFETs. This will allow circuits to be even denser, but at the cost of more complex manufacturing. TSMC expects the transition to occur in 2025 at the earliest. Samsung has already used GAAFET in its 3nm process, which it launched this summer.
New transistors
While with planar transistors the gates only touched the channels on one side (top), with FinFETs they already touched both sides. Only at the GAA, however, are the doors surrounded by channels on all four sides. FinFETs stack channels next to each other horizontally, GAAs will stack them on top of each other. Such transistors can be made smaller, so that the silicon wafer area is used more efficiently. The entire semiconductor troika plans to switch to GAA, but each company calls transistors differently (and there are minor differences between them): GAAFET (TSMC), MBCFET (Samsung), and RibbonFET (Intel).
