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AMD has officially unveiled the first processors with 3D multi-layer chipsets. Milan-X are 7nm Epyc processors with Zen 3 architecture extended by a massive L3 cache, which can significantly speed up tasks dependent on throughput and memory subsystem, for example (but not only) in the field of HPC.
In June, AMD unveiled 3D V-Cache technology, one of the first solutions to use chiplet layering in processors (true, Intel Lakefield was in the world before). This innovation brings significantly expanded L3 cache to Zen 3 processors to improve the performance of this architecture. Yesterday, AMD announced the first processors to have this tiered cache: the Epycy Milan-X supercomputer. We already know when the 3D V-cache will go on sale.
3D V-Cache goes into practice
As the name suggests, the Milan-X is an extension already released and sold Epycu 7003 “Milan”, which has up to 64 Zen 3 cores. Milan-X processors use the same IO chiplet, but the CPU chiplets always have an additional 7nm silicon measuring approximately 6 × 6 mm connected via Direct Bonding and TSV technology, which adds L3 cache capacity, which thus triples.
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Procesory AMD Epyc Milan-X s 3D V-Cache Zdroj: AMD
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Milan-X processors can hold much more data in the cache, which effectively reduces the average RAM latency, because more data requests can be handled from the L3 cache. It could work similarly to a GPU with an RDNA 2 architecture that thanks to the great Infinity Cache they perform as if they have significantly higher memory throughput.
The L3 cache itself probably has a slightly higher latency with added capacity (perhaps about 10%, which would be about 5 cycles), which, however, increases normally when the cache is in one piece of silicon together. But thanks to the higher capacity (hit-rate), 96MB L3 should reduce the overall latency when accessing data from RAM.
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Procesory AMD Epyc Milan-X s 3D V-Cache Zdroj: AMD
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AMD has not yet directly identified specific Epyc Milan-X processor models, but has provided framework parameters. The CPUs will have up to 64 Zen 3 cores, and should work on the same boards as the regular Epycy 7003, only the firmware may need to be updated. The new processor is compatible with SP3 socket and has the same connectivity (128 PCI Express 4.0 lines, eight-channel DDR4-3200 controller). However, while Milan has 256 MB of L3 cache (8 × 32 MB), for Milan-X, AMD states that there is 768 MB of L3 cache per socket / processor. Each of the eight CCX / CPU chipsets that make up the processor therefore has a 96 MB L3 cache. AMD lists up to 804 MB of cache in slides, but this is the sum of a total of 4 MB in L1 individual caches, 32 MB in L2 cache cores and finally 768 MB L3 (in 8 blocks of 96 MB) cache in a 64-core processor.
More: AMD Unveils 3D Chiplet Technology: 64MB 3D V-Cache Processors Mounted on Zen 3 Cores
More about 3D V-Cache was announced in the summer. AMD has now reiterated that Direct Bonding technology is used, where the copper conductors in the TSV are connected directly to the copper conductors of the processor’s metal layers and the cached chiplet, without solder balls between the silicones (“microbumps”). For example, silicon interposers and Intel EMIB and Foveros technologies in the current version use solder, which has worse properties.
According to AMD, Direct Bonding will have up to 15 times higher contact density. The density is even up to 200 times better than interconnection via a common substrate (that is, as the CPU chipsets and IO chips in AMD processors are now interconnected). Perhaps more importantly, there should also be better energy efficiency. In contrast to the solder solution, the copper-copper connection needs less energy and should be more than 3 times more energy efficient.
Significant acceleration for simulations, HPC, technical applications
AMD has not yet said whether the processors will have the same TDP, but the L3 cache also has to improve performance, and in some cases a lot. Where memory performance and the amount of data that can be cached are the biggest constraints, Milan-X could make big improvements.
It could pay a lot in HPC (scientific calculations), but AMD cites as additional examples, for example, working with Synopsys EDA tools in chip development, where Milan-X is to improve performance by 66%.
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AMD Milan-X: 768 MB L3 cache can significantly increase performance in some tasks Zdroj: AMD
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Performance increases will probably not be generally observable in all tasks, in a large number of tasks, if not in most, the difference may not be large at all. There may be cases of no or negative acceleration due to the cache taking a portion of the TDP allocation and L3 latency deteriorating. That’s why AMD will definitely continue to sell the regular version of the Epyce 7003 Milan without this extra cache. Milan-X can probably be seen as a specialized solution.
Issued in the first quarter of 2022
According to AMD, these processors should be realistically available to customers in the first quarter of 2022, and samples are now available. These are available for testing in the Azure cloud, where Microsoft offers HBv3 instances with Milan-X processors. These are probably the first way to try out the performance of Zen 3 with 3D V-Cache.
Microsoft also published a blogpost with benchmarkswhich you can study if you are interested.
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Procesory AMD Epyc Milan-X s 3D V-Cache Zdroj: AMD
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According to unofficial sources The production of CPU chipsets equipped with 3D V-Cache has started or will start in series this month, so it is logical that the final processors will come to the stores a few months later. Perhaps there is some hope that the consumer version, ie Ryzen 5000 or Ryzen 6000 processors with these CPU chipsets set to L3 cache, will be on the market a little earlier, for example at the beginning of Q1 2022. AMD tends to be more aggressive when publishing processors for PCs. However, the company has not announced them yet, because yesterday’s event concerned only servers.
Galerie: Procesory AMD Epyc Milan-X s 3D V-Cache
Resources: AMD, Tom’s Hardware, AnandTech
AMD unveils Milan-X processors with 3D V-Cache. Over 800 MB cache, performance even 50% higher
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