Leaker ExecutableFix has previously released the following assembly, according to which the Genoa generation EPYC server processors will have up to 12 chiplets, which will be set up exactly as the author imagined, if we are to trust the new leaked images. On the other hand, such a placement was, of course, directly offered, although ExecutableFix even hit the proportions of the central I / O chip. That it was not even originally a matter of its invention, but of an assembly created on the basis of specific documents?
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It should be added that these materials on AMD’s plans were to escape on the basis of Gigabyte’s recent server hack, which now does not experience the most famous period. On the one hand, he disputes because of defective resources and now it turns out that the data thieves may have actually decided to publish them after an unsuccessful monetization attempt. But that is good for us again, because AMD has recently revealed little about its plans. –
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We also have more information here, such as the appearance of the SP5 server socket for the next EPYC 7004 Genoa.
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And then there are other images like this, which again shows processors with 12 CCD chipsets in two processors connected by the xGMI bus. This is specifically a table with NUMA nodes, ie a grouping of cores in chipsets, which will be divided into three-chip quadrants.
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It is also confirmed here that the individual CCX (Core Complex) will be eight-core, while the last picture looks at the diagram concerning basically the next 16-core Ryzens, which is the same as in today’s models. We have an I / O chip connected to the Core Complex 0 to N, while the I / O chip itself then takes over the operation of the main operating memory and communication with all other hardware via various buses.
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